DNVN - Keysight Technologies has just launched ChipletPHY Designer 2025, the latest high-speed digital chiplet design solution, suitable for AI and data center applications.
This enhanced software adds simulation capabilities for the Universal Chiplet Interconnect Express™ (UCIe™) 2.0 standard and adds support for the Open Computer Project's Bunch of Wires (BoW) standard. As an advanced system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, simplifying the chip design and manufacturing process.
As AI and data center chips become increasingly complex, reliable communication between chips is critical to ensuring performance.
The market is addressing this challenge with emerging open standards such as UCIe and BoW to define interconnects between chiplets in 2.5D enhanced/3D or overlay/enhanced packaging. By adopting these standards and verifying compliance of chiplets, designers contribute to building an ecosystem of chiplet interoperability, reducing the cost and risk of semiconductor technology development.
Key benefits of Chiplet PHY Designer 2025: Ensure interoperability: Verify that designs meet UCIe 2.0 and BoW standards, enabling seamless integration across advanced packaging ecosystems.
Reduce time to market: Automate simulation and compliance test setup, simplifying the chiplet design process.
Improve design accuracy: Provide insights into signal integrity, bit error rate (BER), and crosstalk analysis, minimizing the risk of redesign and chip manufacturing.
Optimized clock design: Supports advanced clock scheme analysis, such as quarter data rate QDR, for precise synchronization on high-speed connections.
“A year ago, Keysight EDA launched Chiplet PHY Designer as the market’s first pre-silicon validation tool with in-depth modeling and simulation capabilities,” said Hee-Soo Lee, head of customer development for the high-speed digital segment, Keysight EDA. “The tool enables chiplet designers to quickly and accurately verify that their designs meet specifications before manufacturing. The latest release meets emerging standards such as UCIe 2.0 and BoW, and provides new features such as QDR clock mapping and system crosstalk analysis for unidirectional buses. Engineers use Chiplet PHY Designer to save time and reduce errors, ensuring their designs meet performance requirements before manufacturing.” Early adopters of this solution, such as Alphawave Semi, certify that Chiplet PHY Designer ensures seamless operation and interoperability for 2.5D/3D solutions available to their chiplet customers."
Thanh Van
Source: https://doanhnghiepvn.vn/cong-nghe/cong-nghe-ho-tro-thiet-ke-chip-ky-thuat-so-toc-do-cao/20250205033256204
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