This enhanced software adds simulation capabilities for the Universal Chiplet Interconnect Express (UCIe) 2.0 standard and adds support for the Open Computer Project's Bunch of Wires (BoW) standard. As an advanced system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, simplifying the chip design and manufacturing process.
Keysight Technologies now supports various data processing solutions
As AI and data center chips become increasingly complex, ensuring reliable communication between chips is critical to ensuring performance. The market is addressing this challenge with emerging open standards such as UCIe and BoW to define interconnects between chiplets in 2.5D enhanced/3D or overlay/enhanced packaging. By adopting these standards and verifying compliance with chiplets, designers contribute to building an ecosystem of chiplet interoperability, reducing the cost and risk of semiconductor technology development.
The solution also helps shorten time to market, automates simulation and compliance test setup, such as voltage transfer function (VTF), and simplifies the chiplet design process.
“A year ago, Keysight EDA launched Chiplet PHY Designer as the market’s first pre-silicon validation tool with in-depth modeling and simulation capabilities; it enables chiplet designers to quickly and accurately verify that their designs meet specifications before manufacturing,” said Hee-Soo Lee, head of customer development for the high-speed digital segment, Keysight EDA. “The latest release meets emerging standards such as UCIe 2.0 and BoW, and provides new features such as QDR clock mapping and system crosstalk analysis for unidirectional buses. Engineers use Chiplet PHY Designer to save time and reduce errors, ensuring their designs meet performance requirements before manufacturing.”
Source: https://thanhnien.vn/keysight-ra-mat-giai-phap-thiet-ke-chiplet-ky-thuat-so-toc-do-cao-moi-185250205141620491.htm
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